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Macros</h2></td></tr>
<tr><td colspan="2"><div class="groupHeader">Core Register Offsets</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Control Register Bit Definitions</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Interrupt Status/Enable Register Bit Definitions</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Error Register Bit Definitions</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Version Register Bit Definition and Shifts</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Generator/Detector Active Video Size Register Bit Definitions and</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Shift </p>
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<tr class="memitem:ga0e496af33fa4e06a38282742e53610c9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__vtc__v7__0.html#ga0e496af33fa4e06a38282742e53610c9">XVTC_ASIZE_HORI_MASK</a>&#160;&#160;&#160;0x00001FFF</td></tr>
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<tr><td colspan="2"><div class="groupHeader">Generator/Detector Status Bit Definitions</div></td></tr>
<tr class="memitem:gafce16d12d0cda22433f08d8f1cff3c9b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__vtc__v7__0.html#gafce16d12d0cda22433f08d8f1cff3c9b">XVTC_STAT_LOCKED_MASK</a>&#160;&#160;&#160;0x00000001</td></tr>
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<tr><td colspan="2"><div class="groupHeader">Generator/Detector Encoding Register Bit Definitions</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Generator/Detector Polarity Register Bit Definitions</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Generator/Detector Full Vertical Size Register Bit Definitions</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>and Shift </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Generator/Detector Sync/Blank Register Bit Definitions and Shift</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Generator/Detector VBlank/VSync Horizontal Bit Definitions and Shift</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Frame Sync 00 - 15</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">VTC Generator Global Delay Bit Definition and Shift</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Compatibility Macros</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Register Access Macro Definition</div></td></tr>
<tr class="memitem:ga31cab60bdab40dbd0c9762c4de5de734"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__vtc__v7__0.html#ga31cab60bdab40dbd0c9762c4de5de734">XVtc_ReadReg</a>(BaseAddress,  RegOffset)&#160;&#160;&#160;<a class="el" href="group__vtc__v7__0.html#ga8c21088f7fe4f0b05330a7681dd01419">XVtc_In32</a>((BaseAddress) + ((u32)RegOffset))</td></tr>
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<tr class="memitem:ga9c524801283cc3bf9a782c7cbf093098"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__vtc__v7__0.html#ga9c524801283cc3bf9a782c7cbf093098">XVtc_WriteReg</a>(BaseAddress,  RegOffset,  Data)&#160;&#160;&#160;<a class="el" href="group__vtc__v7__0.html#gade6c5f7d09b842234c34bee14fa9d127">XVtc_Out32</a>((BaseAddress) + ((u32)RegOffset), (u32)(Data))</td></tr>
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